PCI Express Terms and Acronyms (Eight)

QWORD, QW Eight bytes. Used in the context of a data payload, the 8 bytes of data must be
on a naturally aligned 8-byte boundary (the least significant 3 bits of the address
are 000b).
Receiver The component that receives Packet information across a Link.
Receiving Port In the context of a specific TLP or DLLP, the Port that receives the Packet on a
given Link.
Reported Error An error subject to the logging and signaling requirements architecturally defined
in this document
Request A Packet used to initiate a transaction sequence. A Request includes operation
code and, in some cases, address and length, data, or other information.
Requester The Function that first introduces a transaction sequence into the PCI Express
domain.
Requester ID The combination of a Requester's Bus Number, Device Number, and Function
Number that uniquely identifies the Requester. With an ARI Requester ID, bits
traditionally used for the Device Number field are used instead to expand the
Function Number field, and the Device Number is implied to be 0.
reserved The contents, states, or information are not defined at this time. Using any
reserved area (for example, packet header bit-fields, configuration register bits) is
not permitted. Reserved register fields must be read only and must return 0 (all
0’s for multi-bit fields) when read. Reserved encodings for register and packet
fields must not be used. Any implementation dependence on a reserved field
value or encoding will result in an implementation that is not PCI Expresscompliant.
The functionality of such an implementation cannot be guaranteed in
this or any future revision of this specification.
Root Complex, RC A defined System Element that includes a Host Bridge, zero or more Root
Complex Integrated Endpoints, zero or more Root Complex Event Collectors,
and one or more Root Ports.
Root Complex
Component A logical aggregation of Root Ports, Root Complex Register Blocks, and Root
Complex Integrated Endpoints.
Root Port A PCI Express Port on a Root Complex that maps a portion of the Hierarchy
through an associated virtual PCI-PCI Bridge.
Set A bit is Set when its value is 1b.
sideband signaling A method for signaling events and conditions using physical signals separate
from the signals forming the Link between two components. All mechanisms
defined in this document can be implemented using in-band signaling, although
in some form factors sideband signaling may be used instead.
slot Used generically to refer to an add-in card slot or module bay.
Split Transaction A single logical transfer containing an initial transaction (the Request) terminated
at the target (the Completer), followed by one or more transactions initiated by
the Completer in response to the Request.
Swap Unconditional Swap. An AtomicOp where a specified value is written to a target
location, and the original value of the location is returned.
Switch A defined System Element that connects two or more Ports to allow Packets to
be routed from one Port to another. To configuration software, a Switch appears
as a collection of virtual PCI-to-PCI Bridges.
Symbol A 10-bit quantity produced as the result of 8b/10b encoding.