PCI Express A Third Generation I/O Interconnect

The high-level requirements for this third generation I/O interconnect are as follows:

Supports multiple market segments and emerging applications: 

• Unifying I/O architecture for desktop, mobile, workstation, server, communications platforms, and embedded devices

Ability to deliver low cost, high volume solutions: 

• Cost at or below PCI cost structure at the system level

Support multiple platform interconnect usages:

• Chip-to-chip, board-to-board via connector or cabling

New mechanical form factors:

• Mobile, PCI-like form factor and modular, cartridge form factor

PCI compatible software model:

• Ability to enumerate and configure PCI Express hardware using PCI system configuration software implementations with no modifications
• Ability to boot existing operating systems with no modifications
• Ability to support existing I/O device drivers with no modifications
• Ability to configure/enable new PCI Express functionality by adopting the PCI configuration paradigm

Performance:

• Low-overhead, low-latency communications to maximize application payload bandwidth and Link efficiency
• High-bandwidth per pin to minimize pin count per device and connector interface
• Scalable performance via aggregated Lanes and signaling frequency

Advanced features:
• Comprehend different data types and ordering rules
• Power management and budgeting
♦ Ability to identify power management capabilities of a given Function
♦ Ability to transition a Function into a specific power state
♦ Ability to receive notification of the current power state of a Function
♦ Ability to generate a request to wakeup from a power-off state of the main power supply
♦ Ability to sequence device power-up to allow graceful platform policy in power
budgeting.
• Ability to support differentiated services, i.e., different qualities of service (QoS)
♦ Ability to have dedicated Link resources per QoS data flow to improve fabric efficiency
and effective application-level performance in the face of head-of-line blocking
♦ Ability to configure fabric QoS arbitration policies within every component
♦ Ability to tag end-to-end QoS with each packet
♦ Ability to create end-to-end isochronous (time-based, injection rate control) solutions
• Hot-Plug and Hot-Swap support
♦ Ability to support existing PCI Hot-Plug and Hot-Swap solutions
♦ Ability to support native Hot-Plug and Hot-Swap solutions (no sideband signals
required)
♦ Ability to support a unified software model for all form factors
• Data Integrity
♦ Ability to support Link-level data integrity for all types of transaction and Data Link
packets
♦ Ability to support end-to-end data integrity for high availability solutions
• Error Handling
♦ Ability to support PCI-level error handling
♦ Ability to support advanced error reporting and handling to improve fault isolation and
recovery solutions
• Process Technology Independence
♦ Ability to support different DC common mode voltages at Transmitter and Receiver
• Ease of Testing
♦ Ability to test electrical compliance via simple connection to test equipment

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