PCI Express Terms and Acronyms (Six)

FLR or
Function Level Reset A mechanism for resetting a specific Endpoint Function (see Section 6.6.2).
Fundamental Reset A hardware mechanism for setting or returning all Port states to the initial
conditions specified in this document (see Section 6.6).
header A set of fields that appear at the front of a Packet that contain the information
required to determine the characteristics and purpose of the Packet.
Hierarchy The tree structured PCI Express I/O interconnect topology.
hierarchy domain The part of a Hierarchy originating from a single Root Port.
Host Bridge The part of a Root Complex that connects a host CPU or CPUs to a Hierarchy.
hot reset A reset propagated in-band across a Link using a Physical Layer mechanism.
in-band signaling A method for signaling events and conditions using the Link between two
components, as opposed to the use of separate physical (sideband) signals. All
mechanisms defined in this document can be implemented using in-band
signaling, although in some form factors sideband signaling may be used
instead.
Ingress Port Receiving Port; that is, the Port that accepts incoming traffic.
Internal Error An error associated with a PCI Express interface that occurs within a component
and which may not be attributable to a packet or event on the PCI Express
interface itself or on behalf of transactions initiated on PCI Express.
I/O Space One of the four address spaces of the PCI Express architecture. Identical to the
I/O Space defined in the PCI Local Bus Specification, Revision 3.0.
isochronous Data associated with time-sensitive applications, such as audio or video
applications.
invariant A field of a TLP header that contains a value that cannot legally be modified as
the TLP flows through the PCI Express fabric.
Lane A set of differential signal pairs, one pair for transmission and one pair for
reception. A by-N Link is composed of N Lanes.
Layer A unit of distinction applied to this specification to help clarify the behavior of key
elements. The use of the term Layer does not imply a specific implementation.
Link The collection of two Ports and their interconnecting Lanes. A Link is a dualsimplex
communications path between two components.
Local TLP Prefix A TLP Prefix that is carried along with a TLP on a single Link. See
Section 2.2.10.1.
Logical Bus The logical connection among a collection of Devices that have the same Bus
Number in Configuration Space.
Logical Idle A period of one or more Symbol Times when no information (TLPs, DLLPs, or
any special Symbol) is being transmitted or received. Unlike Electrical Idle,
during Logical Idle the idle Symbol is being transmitted and received.
Malformed Packet A TLP that violates specific TLP formation rules as defined in this specification.
Memory Space One of the four address spaces of the PCI Express architecture. Identical to the
Memory Space defined in PCI 3.0.
Message A TLP used to communicate information outside of the Memory, I/O, and
Configuration Spaces.